As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as multi-gate field effect transistor (FET) including a fin FET (FinFET) and a gate-all-around (GAA) FET. In a FinFET, a gate electrode is adjacent to three side surfaces of a channel region with a gate dielectric layer interposed therebetween. Because the gate structure surrounds the fin on three surfaces, the transistor essentially has the gates controlling the current through the fin or channel region. However, the fourth side that is the bottom part of the channel region is far away from gate electrode and this is not under close gate control. Different from FinFET, in a GAA FET all side surfaces of the channel region are surrounded by the gate electrode, which allows for fuller depletion in the channel region and results in less short-channel effects due to a steeper sub-threshold current swing (SS) and smaller drain induced barrier lower (DIBL).
Although existing GAA FET devices and methods of fabricating GAA FET devices have been generally adequate for their intended purpose, they have not been entirely satisfactory in all aspects.